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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>fr.tpt.mem4csd.sefa.build.main</name>
<comment></comment>
<projects>
</projects>
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<?xml version="1.0" encoding="UTF-8"?>
<project xmlns="http://maven.apache.org/POM/4.0.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://maven.apache.org/POM/4.0.0 http://maven.apache.org/xsd/maven-4.0.0.xsd">
<properties>
<tycho-version>1.0.0</tycho-version>
<platform-version-name>2018-12</platform-version-name>
<eclipse-site>http://download.eclipse.org/releases/${platform-version-name}</eclipse-site>
</properties>
<modelVersion>4.0.0</modelVersion>
<groupId>sefa</groupId>
<artifactId>fr.tpt.mem4csd.sefa.build.main</artifactId>
<version>0.0.1-SNAPSHOT</version>
<packaging>pom</packaging>
<modules>
<module>../fr.tpt.mem4csd.sefa.updatesite</module>
<module>../fr.tpt.mem4csd.sefa.trajectory</module>
<module>../fr.tpt.mem4csd.sefa.feature</module>
<module>../fr.tpt.mem4csd.sefa.examples</module>
</modules>
<repositories>
<repository>
<id>${platform-version-name}</id>
<layout>p2</layout>
<url>${eclipse-site}</url>
</repository>
<repository>
<id>osate</id>
<layout>p2</layout>
<url>http://www.aadl.info/aadl/osate/stable/latest/updates/</url>
</repository>
</repositories>
<build>
<plugins>
<plugin>
<groupId>org.apache.maven.plugins</groupId>
<artifactId>maven-jarsigner-plugin</artifactId>
<version>1.4</version>
<executions>
<execution>
<id>sign</id>
<goals>
<goal>sign</goal>
</goals>
</execution>
</executions>
</plugin>
<plugin>
<groupId>org.eclipse.tycho</groupId>
<artifactId>tycho-maven-plugin</artifactId>
<version>${tycho-version}</version>
<extensions>true</extensions>
</plugin>
<plugin>
<artifactId>maven-eclipse-plugin</artifactId>
<version>2.9</version>
<configuration>
<pde>true</pde>
</configuration>
</plugin>
</plugins>
</build>
</project>
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>fr.tpt.mem4csd.sefa.example</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
</natures>
</projectDescription>
property set AFDX_Properties is
------------------------------------------------------------------
--- 1. Virtual Link Properties
------------------------------------------------------------------
-- BAG - Bandwidth Allocation Gap
-- The End-System controls the transmission flow for each VL
-- in accordance with the BAG (traffic shaping).
-- The Switch verifies the BAG (traffic policing).
-- CONSTRAINTS: power of 2 between 1 ms and 128 ms.
-- MANDATORY: for each AFDX virtual link
BAG : TIME applies to (virtual bus);
Deadline: Time applies to (virtual bus);
-- Maximum VL frame size
-- MANDATORY: for each AFDX virtual link
Lmax : AADLINTEGER 64 Bytes .. 1518 Bytes units SIZE_UNITS applies to (virtual bus);
-- Minimum VL frame size
-- OPTIONAL: 64 bytes by default
Lmin : AADLINTEGER 64 Bytes .. 1518 Bytes units SIZE_UNITS => 64 Bytes applies to (virtual bus);
-- The maximum time between the reception of two redundant frames
-- MANDATORY: for each AFDX virtual link
SkewMax : TIME applies to (virtual bus);
-- Send frames on both ports A and B, but delay the transmission on one of the ports by the skew delay.
-- CONSTRAINTS: only one of the properties should be more than zero
-- OPTIONAL: No skew delay by default
SkewDelayA : TIME => 0 ms applies to (virtual bus);
SkewDelayB : TIME => 0 ms applies to (virtual bus);
-- Virtual Link Identifier: 16 bit
-- CONSTRAINTS: unique across AFDX network
-- OPTIONAL: can be generated automatically
VLID : AADLINTEGER 0 .. 65535 applies to (virtual bus);
------------------------------------------------------------------
--- 2. End System Properties
------------------------------------------------------------------
-- Sub-VL defines order of delivery of messages via virtual link.
-- Each Sub-VL has a dedicated FIFO queue, that queues are read on a round robin basis by the output VL FIFO queue.
-- Sub-VL is an optional feature of AFDX.
-- A VL FIFO queue should be able to manage at most 4 Sub-VL FIFO queues.
-- OPTIONAL: by default all messages go via the only sub-VL
Max_Supported_SubVLs : AADLINTEGER => 1 applies to (device,system,processor);
-- List of supported speeds
-- CONSTRAINTS: 10 MBpersec,100 MBpersec or 1000 MBpersec
-- OPTIONAL: mandatory to be able check consistency
-- Makes sense for bus accesses of end system and switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in device for all ports at once
Supported_Port_Speeds : inherit list of Data_Volume applies to (device,system,processor,bus access);
-- Speed of the physical port
-- CONSTRAINTS: should be in compliance with Supported_Port_Speeds of End System and Switch
-- CONSTRAINTS: must be defined at least on one side of each AFDX wire
-- OPTIONAL: see constraints above
-- Makes sense for bus accesses of end system and switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in one place for the whole system
portSpeed : inherit Data_Volume applies to (device,system,bus access);
-- Network Selector
-- OPTIONAL: by default we consider the only network keeping in mind the second one is a copy
networkSelector : enumeration (A, B) applies to (device, bus access, virtual bus);
------------------------------------------------------------------
--- 3. Partititon Properties
------------------------------------------------------------------
-- Sub-VL defines order of delivery of messages via virtual link.
-- Each Sub-VL has a dedicated FIFO queue, that queues are read on a round robin basis by the output VL FIFO queue.
-- Sub-VL is an optional feature of AFDX.
-- A VL FIFO queue should be able to manage at most 4 Sub-VL FIFO queues.
-- CONSTRAINTS: less or equal Max_Supported_SubVLs of AFDX End System
-- CONSTRAINTS: applied to output ports only
-- CONSTRAINTS: if a port has subVL all other ports bound to the same virtual link have to have subVL as well
-- OPTIONAL: by default all messages go via the only sub-VL
SubVL : AADLINTEGER applies to (port);
-- UDP Port
-- CONSTRAINTS: for output ports it is unique across all output ports of the partition
-- CONSTRAINTS: for input ports it is unique across all input ports of the partition
-- OPTIONAL: can be generated automatically
UDP : AADLINTEGER 1 .. 65535 applies to (port);
-- Partition ID: 8 bits
-- It is used to build source (or unicast destination) IP address of partition
-- CONSTRAINTS: unique across system (may be in pair with User_Defined_ID?)
-- OPTIONAL: can be generated automatically
PartitionID : AADLINTEGER 0 .. 255 applies to (virtual processor,process);
------------------------------------------------------------------
--- 4. AFDX Switch Properties
------------------------------------------------------------------
-- AFDX Switch Configuration Table
-- CONSTRAINTS: applicable to AFDX switches only
-- CONSTRAINTS: virtual links have to be bound to the switch
-- CONSTRAINTS: should contains entry for any virtual link bound to the switch
-- OPTIONAL: requires for configuration generation and detailed analysis
VL_Route_Table : list of record (
vl : reference (virtual bus); -- MANDATORY: Virtual link
in_port : reference (bus access); -- OPTIONAL: can be evaluated from VL bindings
out_ports : list of reference (bus access); -- OPTIONAL: can be evaluated from VL bindings
jitter : TIME; -- MANDATORY: Maximum allowed Jitter
priority : enumeration (high, low); -- MANDATORY: priority
accountingPolicy : enumeration (byte, frame); -- MANDATORY: policy
sharedAccountId : aadlstring; -- OPTIONAL: specifying if this account is shared or not
) applies to (device,system);
-- Output Buffer Size for High/Low Priority VLs
-- CONSTRAINTS: applicable to ports of AFDX switches only
-- OPTIONAL: 1 by default
highPriorityQSize : aadlinteger 0 .. Max_Queue_Size => 1 applies to (bus access);
lowPriorityQSize : aadlinteger 0 .. Max_Queue_Size => 1 applies to (bus access);
-- An output port should not transmit frames that are older than "max delay".
-- The maximum delay parameter of a frame on a given port is defined as the maximum elapsed time between the two following events:
-- 1. Arrival of the last bit of a frame on the input port of a switch
-- 2. Exit of this last bit of the frame from the given output port of the switch
-- CONSTRAINTS: applicable to output bus access of AFDX switches only
-- MANDATORY: for each connected output port
-- Makes sense for bus accesses of AFDX switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in one place for the whole switch
maxDelay : inherit TIME applies to (bus access,device,system);
minDelay : inherit TIME applies to (bus access,device,system);
jitter : inherit TIME applies to (virtual bus);
priority : aadlinteger applies to (virtual bus);
-- List of supported speeds
-- CONSTRAINTS: 10 MBpersec,100 MBpersec or 1000 MBpersec
-- OPTIONAL: mandatory to be able check consistency
-- Defined in section for end systems
-- Makes sense for bus accesses of end system and switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in device for all ports at once
-- Supported_Port_Speeds : inherit list of Data_Volume applies to (device,system,processor,bus access);
-- Speed of the physical port
-- CONSTRAINTS: should be in compliance with Supported_Port_Speeds of End System and Switch
-- CONSTRAINTS: must be defined at least on one side of each AFDX wire
-- OPTIONAL: see constraints above
-- Makes sense for bus accesses of end system and switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in one place for the whole system
-- Defined in section for end systems
-- portSpeed : inherit Data_Volume applies to (device,system,bus access);
end AFDX_Properties;
------------------------------------------------------------------
-- A library of AADL components to be used to model AFDX networks.
--
------------------------------------------------------------------
--------------------List of changes-------------------------------
------------------------------------------------------------------
------------------------------------------------------------------
-- Version 1.0. (20 Sep 2015)
-- Initial revision for 2015 Fall AADL meeting
-- Alexey Khoroshilov (ISPRAS)
------------------------------------------------------------------
PACKAGE AFDX
Public
WITH AFDX_Properties;
------------------------------------------------------------------
--- 1. Hardware Components
------------------------------------------------------------------
------------------------------------------------------------------
--- 1.1 AFDXWire
------------------------------------------------------------------
BUS Wire
END Wire;
------------------------------------------------------------------
--- 1.2 AFDXSwitch
------------------------------------------------------------------
ABSTRACT Switch
END Switch;
------------------------------------------------------------------
--- 1.2 AFDX End System
------------------------------------------------------------------
ABSTRACT End_System
FEATURES
afdx : REQUIRES BUS ACCESS Wire;
END End_System;
------------------------------------------------------------------
--- 2. AFDX Network Configuration
------------------------------------------------------------------
------------------------------------------------------------------
--- 2.1 AFDX Network
------------------------------------------------------------------
VIRTUAL BUS Network
annex pycl {**
@constraint("Virtual Link Identifier should be unique across AFDX network")
def vlids_is_unique(self,vlids):
from collections import Counter
cnts = Counter(vlids.values())
cnts.subtract(Counter(cnts.keys()))
if len(cnts)!=0:
vlids = {str(vl):vlids[vl] for vl in vlids if vlids[vl] in cnts.keys()}
self.info('There are nonunique elements:'+str(vlids))
return False
return True
**};
END Network;
VIRTUAL BUS IMPLEMENTATION Network.i
END Network.i;
------------------------------------------------------------------
--- 2.2 AFDX Virtual Link
------------------------------------------------------------------
VIRTUAL BUS Virtual_Link
annex pycl {**
@constraint("BAG is MANDATORY for each AFDX virtual link")
def bag_is_mandatory(self):
return self.hasProperty('AFDX_Properties::BAG')
@constraint("BAG is power of 2 between 1 ms and 128 ms")
def bag_is_power_of_two(self):
from AADL_Project.Time_Units import ms
if not self.properties['AFDX_Properties::BAG'] in ((2**x)*ms for x in range(7)):
self.info(str(self.properties['AFDX_Properties::BAG'])+' is not power of 2 between 1 ms and 128 ms')
return False
return True
@constraint("only one of SkewDelayA and SkewDelayB should be more than zero")
def skew_delay_zero(self):
return self.properties['AFDX_Properties::SkewDelayA']==0 \
or self.properties['AFDX_Properties::SkewDelayB']==0
**};
END Virtual_Link;
VIRTUAL BUS IMPLEMENTATION Virtual_Link.i
END Virtual_Link.i;
VIRTUAL BUS IMPLEMENTATION Virtual_Link.dup
SUBCOMPONENTS
netA : VIRTUAL BUS Virtual_Link;
netB : VIRTUAL BUS Virtual_Link;
END Virtual_Link.dup;
END AFDX;
This diff is collapsed.
PACKAGE Basic_AFDX_Model
Public
WITH AFDX_Properties;
WITH AFDX;
WITH Software_Layer;
AFDX_Network renames VIRTUAL BUS AFDX::Network;
--- AFDX_Model
SYSTEM Basic_AFDX_Model
END Basic_AFDX_Model;
SYSTEM IMPLEMENTATION Basic_AFDX_Model.i
SUBCOMPONENTS
HW_Platform : SYSTEM HW_Platform.i;
Software_Layer : SYSTEM Software_Layer::Software_Layer.i;
-- ARINC-653 Configuration
P_1 : VIRTUAL PROCESSOR;
P_2 : VIRTUAL PROCESSOR;
P_3 : VIRTUAL PROCESSOR;
P_4 : VIRTUAL PROCESSOR;
-- AFDX Configuration
AFDX_Network : VIRTUAL BUS AFDX_Network.i;
PROPERTIES
-- Network speed defined for the whole network here
AFDX_Properties::portSpeed => 100 MBytesps;
-- Maps processes to processors
Actual_Processor_Binding => (reference(P_1)) applies to Software_Layer.P_1;
Actual_Processor_Binding => (reference(P_2)) applies to Software_Layer.P_2;
Actual_Processor_Binding => (reference(P_3)) applies to Software_Layer.P_3;
Actual_Processor_Binding => (reference(P_4)) applies to Software_Layer.P_4;
Actual_Processor_Binding => (reference(HW_Platform.CPM_1.CPU)) applies to P_1;
Actual_Processor_Binding => (reference(HW_Platform.CPM_2.CPU)) applies to P_2;
Actual_Processor_Binding => (reference(HW_Platform.CPM_3.CPU)) applies to P_3;
Actual_Processor_Binding => (reference(HW_Platform.CPM_3.CPU)) applies to P_4;
-- Define virtual link configuration
Actual_Connection_Binding => (reference(HW_Platform.CPM_1.AFDX_ES),
reference(HW_Platform.WIRE_1),reference(HW_Platform.SW_1),
reference(HW_Platform.WIRE_3),reference(HW_Platform.CPM_2.AFDX_ES))
applies to AFDX_Network.VL1;
Actual_Connection_Binding => (reference(HW_Platform.CPM_2.AFDX_ES),
reference(HW_Platform.WIRE_3),reference(HW_Platform.SW_1),
reference(HW_Platform.WIRE_2),reference(HW_Platform.SW_2),
reference(HW_Platform.WIRE_4),reference(HW_Platform.CPM_3.AFDX_ES))
applies to AFDX_Network.VL2;
Actual_Connection_Binding => (reference(HW_Platform.CPM_1.AFDX_ES),
reference(HW_Platform.WIRE_1),reference(HW_Platform.SW_1),
reference(HW_Platform.WIRE_2),reference(HW_Platform.SW_2),
reference(HW_Platform.WIRE_3),reference(HW_Platform.CPM_2.AFDX_ES),
reference(HW_Platform.WIRE_4),reference(HW_Platform.CPM_3.AFDX_ES))
applies to AFDX_Network.VL3;
-- Map connections to virtual links
Actual_Connection_Binding => (reference(HW_Platform.CPM_1.PCI_BUS),
reference(AFDX_Network.VL1),
reference(HW_Platform.CPM_2.PCI_BUS))
applies to Software_Layer.CQ_1_2;
Actual_Connection_Binding => (reference(HW_Platform.CPM_1.PCI_BUS),
reference(AFDX_Network.VL3),
reference(HW_Platform.CPM_2.PCI_BUS))
applies to Software_Layer.CS_1_2;
Actual_Connection_Binding => (reference(HW_Platform.CPM_1.PCI_BUS),
reference(AFDX_Network.VL2),
reference(HW_Platform.CPM_2.PCI_BUS))
applies to Software_Layer.C_2_3;
Actual_Connection_Binding => (reference(HW_Platform.CPM_1.PCI_BUS),
reference(AFDX_Network.VL3),
reference(HW_Platform.CPM_3.PCI_BUS))
applies to Software_Layer.C_1_3;
Actual_Connection_Binding => (reference(HW_Platform.CPM_1.PCI_BUS),
reference(AFDX_Network.VL3),
reference(HW_Platform.CPM_3.PCI_BUS))
applies to Software_Layer.C_1_4;
Actual_Connection_Binding => (reference(HW_Platform.CPM_2.PCI_BUS),
reference(AFDX_Network.VL2),
reference(HW_Platform.CPM_3.PCI_BUS))
applies to Software_Layer.C_2_4;
-- Map AFDX Network to HW elements
Actual_Connection_Binding => (reference(HW_Platform.CPM_1.AFDX_ES),
reference(HW_Platform.CPM_2.AFDX_ES),
reference(HW_Platform.CPM_3.AFDX_ES),
reference(HW_Platform.WIRE_1),reference(HW_Platform.WIRE_2),
reference(HW_Platform.WIRE_3),reference(HW_Platform.WIRE_4),
reference(HW_Platform.SW_1),reference(HW_Platform.SW_2))
applies to AFDX_Network;
-- Switch configuration
AFDX_Properties::VL_Route_Table => ([
vl => reference (AFDX_Network.VL1);
jitter => 8 us;
priority => high;
accountingPolicy => frame;
],
[
vl => reference (AFDX_Network.VL2);
jitter => 16 us;
priority => low;
accountingPolicy => frame;
],
[
vl => reference (AFDX_Network.VL3);
jitter => 16 us;
priority => high;
accountingPolicy => frame;
]) applies to HW_Platform.SW_1;
AFDX_Properties::VL_Route_Table => ([
vl => reference (AFDX_Network.VL2);
jitter => 16 us;
priority => low;
accountingPolicy => frame;
],
[
vl => reference (AFDX_Network.VL3);
jitter => 16 us;
priority => high;
accountingPolicy => frame;
]) applies to HW_Platform.SW_2;
END Basic_AFDX_Model.i;
--- 1. HW_Platform
SYSTEM HW_Platform
END HW_Platform;
SYSTEM IMPLEMENTATION HW_Platform.i
SUBCOMPONENTS
CPM_1 : SYSTEM Module.i; -- Processor or System
CPM_2 : SYSTEM Module.i; -- Processor or System
CPM_3 : SYSTEM Module.i; -- Processor or System
WIRE_1 : BUS AFDX::Wire; -- Bus
WIRE_2 : BUS AFDX::Wire; -- Bus
WIRE_3 : BUS AFDX::Wire; -- Bus
WIRE_4 : BUS AFDX::Wire; -- Bus
SW_1 : DEVICE AFDXSwitch_4p; -- Device or System
SW_2 : DEVICE AFDXSwitch_4p; -- Device or System
CONNECTIONS
WIRE_1_CPM_1: BUS ACCESS WIRE_1->CPM_1.afdx;
WIRE_1_SW_1: BUS ACCESS WIRE_1->SW_1.afdx_p1;
WIRE_3_SW_1: BUS ACCESS WIRE_3->SW_1.afdx_p3;
WIRE_1_CPM_2: BUS ACCESS WIRE_3->CPM_2.afdx;
WIRE_2_SW_1: BUS ACCESS WIRE_2->SW_1.afdx_p4;
WIRE_2_SW_2: BUS ACCESS WIRE_2->SW_2.afdx_p1;
WIRE_4_SW_2: BUS ACCESS WIRE_4->SW_2.afdx_p4;
WIRE_4_CPM_3: BUS ACCESS WIRE_4->CPM_3.afdx;
END HW_Platform.i;
--- 1.1 Module
SYSTEM Module
FEATURES
afdx : REQUIRES BUS ACCESS AFDX::Wire;
END Module;
SYSTEM IMPLEMENTATION Module.i
SUBCOMPONENTS
CPU : PROCESSOR CPU_with_PCI;
AFDX_ES : DEVICE AFDX_Card;
PCI_BUS : BUS;
CONNECTIONS
CPU_PCI: BUS ACCESS PCI_BUS->CPU.pci;
AFDX_ES_PCI: BUS ACCESS PCI_BUS->AFDX_ES.pci;
AFDX_EXT: BUS ACCESS AFDX_ES.afdx->afdx;
END Module.i;
--- 1.2 CPU_with_PCI
PROCESSOR CPU_with_PCI
FEATURES
pci : REQUIRES BUS ACCESS;
END CPU_with_PCI;
-- 1.3 AFDX_Card
DEVICE AFDX_Card EXTENDS AFDX::End_System
FEATURES
pci : REQUIRES BUS ACCESS;
PROPERTIES
AFDX_Properties::Supported_Port_Speeds => (100 MBytesps);
END AFDX_Card;
--- 1.4 AFDXSwitch - An implementation with 4 port
DEVICE AFDXSwitch_4p EXTENDS AFDX::Switch
FEATURES
afdx_p1 : REQUIRES BUS ACCESS AFDX::Wire;
afdx_p2 : REQUIRES BUS ACCESS AFDX::Wire;
afdx_p3 : REQUIRES BUS ACCESS AFDX::Wire;
afdx_p4 : REQUIRES BUS ACCESS AFDX::Wire;
PROPERTIES
AFDX_Properties::Supported_Port_Speeds => (10 MBytesps,100 MBytesps);
END AFDXSwitch_4p;
--- 2. AFDX Network Configuration
VIRTUAL BUS IMPLEMENTATION AFDX_Network.i
SUBCOMPONENTS
VL1 : VIRTUAL BUS AFDX::Virtual_Link;
VL2 : VIRTUAL BUS AFDX::Virtual_Link;
VL3 : VIRTUAL BUS AFDX::Virtual_Link;
PROPERTIES
-- Setup virtual links configuration
AFDX_Properties::BAG => 1 ms applies to VL1,VL2,VL3;
AFDX_Properties::Lmax => 1518 Bytes applies to VL1;
AFDX_Properties::Lmax => 512 Bytes applies to VL2,VL3;
AFDX_Properties::SkewMax => 1 ms applies to VL1,VL2,VL3;
END AFDX_Network.i;
END Basic_AFDX_Model;
PACKAGE AFDX_Unconfigured
Public
WITH AFDX_Properties;
WITH AFDX;
WITH Software_Layer;
-- AFDX_Model
SYSTEM AFDX_PreSynthesis
END AFDX_PreSynthesis;
SYSTEM IMPLEMENTATION AFDX_PreSynthesis.i
SUBCOMPONENTS
Software_Layer : SYSTEM Software_Layer::Software_Layer.i;
HW_Platform : SYSTEM HW_Platform.i;
-- ARINC-653 Configuration
P_1 : VIRTUAL PROCESSOR;
P_2 : VIRTUAL PROCESSOR;
P_3 : VIRTUAL PROCESSOR;
P_4 : VIRTUAL PROCESSOR;
-- AFDX Configuration
AFDX_Network : VIRTUAL BUS AFDX::Network;
PROPERTIES
-- Maps processes to processors
Actual_Processor_Binding => (reference(P_1)) applies to Software_Layer.P_1;
Actual_Processor_Binding => (reference(P_2)) applies to Software_Layer.P_2;
Actual_Processor_Binding => (reference(P_3)) applies to Software_Layer.P_3;
Actual_Processor_Binding => (reference(P_4)) applies to Software_Layer.P_4;
Actual_Processor_Binding => (reference(HW_Platform.CPM_1.CPU)) applies to P_1;
Actual_Processor_Binding => (reference(HW_Platform.CPM_2.CPU)) applies to P_2;
Actual_Processor_Binding => (reference(HW_Platform.CPM_3.CPU)) applies to P_3;
Actual_Processor_Binding => (reference(HW_Platform.CPM_3.CPU)) applies to P_4;
-- Map connections to virtual links
Actual_Connection_Binding => (reference(AFDX_Network))
applies to Software_Layer.CQ_1_2, Software_Layer.CS_1_2,
Software_Layer.C_2_3, Software_Layer.C_1_3,
Software_Layer.C_1_4, Software_Layer.C_2_4;
-- Map AFDX Network to HW elements
Actual_Connection_Binding => (reference(HW_Platform.CPM_1.AFDX_ES),
reference(HW_Platform.CPM_2.AFDX_ES),
reference(HW_Platform.CPM_3.AFDX_ES),
reference(HW_Platform.WIRE_1),reference(HW_Platform.WIRE_2),
reference(HW_Platform.WIRE_3),reference(HW_Platform.WIRE_4),
reference(HW_Platform.SW_1),reference(HW_Platform.SW_2))
applies to AFDX_Network;
END AFDX_PreSynthesis.i;
-- 1. HW_Platform
SYSTEM HW_Platform
END HW_Platform;
SYSTEM IMPLEMENTATION HW_Platform.i
SUBCOMPONENTS
CPM_1 : SYSTEM Module.i; -- Processor or System
CPM_2 : SYSTEM Module.i; -- Processor or System
CPM_3 : SYSTEM Module.i; -- Processor or System
WIRE_1 : BUS AFDX::Wire; -- Bus
WIRE_2 : BUS AFDX::Wire; -- Bus
WIRE_3 : BUS AFDX::Wire; -- Bus
WIRE_4 : BUS AFDX::Wire; -- Bus
SW_1 : DEVICE AFDXSwitch_4p; -- Device or System
SW_2 : DEVICE AFDXSwitch_4p; -- Device or System
CONNECTIONS
WIRE_1_CPM_1: BUS ACCESS WIRE_1->CPM_1.afdx;
WIRE_1_SW_1: BUS ACCESS WIRE_1->SW_1.afdx_p1;
WIRE_3_SW_1: BUS ACCESS WIRE_3->SW_1.afdx_p3;
WIRE_1_CPM_2: BUS ACCESS WIRE_3->CPM_2.afdx;
WIRE_2_SW_1: BUS ACCESS WIRE_2->SW_1.afdx_p4;
WIRE_2_SW_2: BUS ACCESS WIRE_2->SW_2.afdx_p1;
WIRE_4_SW_2: BUS ACCESS WIRE_4->SW_2.afdx_p4;
WIRE_4_CPM_3: BUS ACCESS WIRE_4->CPM_3.afdx;
END HW_Platform.i;
-- 1.1 Module
SYSTEM Module
FEATURES
afdx : REQUIRES BUS ACCESS AFDX::Wire;
END Module;
SYSTEM IMPLEMENTATION Module.i
SUBCOMPONENTS
CPU : PROCESSOR CPU_with_PCI;
AFDX_ES : DEVICE AFDX_Card;
PCI_BUS : BUS;
CONNECTIONS
CPU_PCI: BUS ACCESS PCI_BUS->CPU.pci;
AFDX_ES_PCI: BUS ACCESS PCI_BUS->AFDX_ES.pci;
AFDX_EXT: BUS ACCESS AFDX_ES.afdx->afdx;
END Module.i;
-- 1.2 CPU_with_PCI
PROCESSOR CPU_with_PCI
FEATURES
pci : REQUIRES BUS ACCESS;
END CPU_with_PCI;
-- 1.3 AFDX_Card
DEVICE AFDX_Card EXTENDS AFDX::End_System
FEATURES
pci : REQUIRES BUS ACCESS;
PROPERTIES
AFDX_Properties::Supported_Port_Speeds => (100 MBytesps);
END AFDX_Card;
-- 1.4 AFDXSwitch - An implementation with 4 port
DEVICE AFDXSwitch_4p EXTENDS AFDX::Switch
FEATURES
afdx_p1 : REQUIRES BUS ACCESS AFDX::Wire;
afdx_p2 : REQUIRES BUS ACCESS AFDX::Wire;
afdx_p3 : REQUIRES BUS ACCESS AFDX::Wire;
afdx_p4 : REQUIRES BUS ACCESS AFDX::Wire;
PROPERTIES
AFDX_Properties::Supported_Port_Speeds => (10 MBytesps,100 MBytesps);
END AFDXSwitch_4p;
END AFDX_Unconfigured;
------------------------------------------------------------------
-- A property set for AADL models of AFDX networks.
--
------------------------------------------------------------------
--------------------List of changes-------------------------------
------------------------------------------------------------------
------------------------------------------------------------------
-- Version 1.0. (1 Oct 2014)
-- Initial revision for 2014 Fall AADL meeting
-- Alexey Khoroshilov (ISPRAS)
------------------------------------------------------------------
property set AFDX_Properties2 is
------------------------------------------------------------------
--- 1. Virtual Link Properties
------------------------------------------------------------------
-- BAG - Bandwidth Allocation Gap
-- The End-System controls the transmission flow for each VL
-- in accordance with the BAG (traffic shaping).
-- The Switch verifies the BAG (traffic policing).
-- CONSTRAINTS: power of 2 between 1 ms and 128 ms.
-- MANDATORY: for each AFDX virtual link
BAG : TIME applies to (virtual bus);
-- Maximum VL frame size
-- MANDATORY: for each AFDX virtual link
Lmax : AADLINTEGER 64 Bytes .. 1518 Bytes units SIZE_UNITS applies to (virtual bus);
-- Minimum VL frame size
-- OPTIONAL: 64 bytes by default
Lmin : AADLINTEGER 64 Bytes .. 1518 Bytes units SIZE_UNITS => 64 Bytes applies to (virtual bus);
-- The maximum time between the reception of two redundant frames
-- MANDATORY: for each AFDX virtual link
SkewMax : TIME applies to (virtual bus);
-- Send frames on both ports A and B, but delay the transmission on one of the ports by the skew delay.
-- CONSTRAINTS: only one of the properties should be more than zero
-- OPTIONAL: No skew delay by default
SkewDelayA : TIME => 0 ms applies to (virtual bus);
SkewDelayB : TIME => 0 ms applies to (virtual bus);
-- Virtual Link Identifier: 16 bit
-- CONSTRAINTS: unique across AFDX network
-- OPTIONAL: can be generated automatically
VLID : AADLINTEGER 0 .. 65535 applies to (virtual bus);
------------------------------------------------------------------
--- 2. End System Properties
------------------------------------------------------------------
-- Sub-VL defines order of delivery of messages via virtual link.
-- Each Sub-VL has a dedicated FIFO queue, that queues are read on a round robin basis by the output VL FIFO queue.
-- Sub-VL is an optional feature of AFDX.
-- A VL FIFO queue should be able to manage at most 4 Sub-VL FIFO queues.
-- OPTIONAL: by default all messages go via the only sub-VL
Max_Supported_SubVLs : AADLINTEGER => 1 applies to (device,system,processor);
-- List of supported speeds
-- CONSTRAINTS: 10 MBpersec,100 MBpersec or 1000 MBpersec
-- OPTIONAL: mandatory to be able check consistency
-- Makes sense for bus accesses of end system and switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in device for all ports at once
Supported_Port_Speeds : inherit list of Data_Volume applies to (device,system,processor,bus access);
-- Speed of the physical port
-- CONSTRAINTS: should be in compliance with Supported_Port_Speeds of End System and Switch
-- CONSTRAINTS: must be defined at least on one side of each AFDX wire
-- OPTIONAL: see constraints above
-- Makes sense for bus accesses of end system and switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in one place for the whole system
portSpeed : inherit Data_Volume applies to (device,system,bus access);
-- Network Selector
-- OPTIONAL: by default we consider the only network keeping in mind the second one is a copy
networkSelector : enumeration (A, B) applies to (device, bus access, virtual bus);
------------------------------------------------------------------
--- 3. Partititon Properties
------------------------------------------------------------------
-- Sub-VL defines order of delivery of messages via virtual link.
-- Each Sub-VL has a dedicated FIFO queue, that queues are read on a round robin basis by the output VL FIFO queue.
-- Sub-VL is an optional feature of AFDX.
-- A VL FIFO queue should be able to manage at most 4 Sub-VL FIFO queues.
-- CONSTRAINTS: less or equal Max_Supported_SubVLs of AFDX End System
-- CONSTRAINTS: applied to output ports only
-- CONSTRAINTS: if a port has subVL all other ports bound to the same virtual link have to have subVL as well
-- OPTIONAL: by default all messages go via the only sub-VL
SubVL : AADLINTEGER applies to (port);
-- UDP Port
-- CONSTRAINTS: for output ports it is unique across all output ports of the partition
-- CONSTRAINTS: for input ports it is unique across all input ports of the partition
-- OPTIONAL: can be generated automatically
UDP : AADLINTEGER 1 .. 65535 applies to (port);
-- Partition ID: 8 bits
-- It is used to build source (or unicast destination) IP address of partition
-- CONSTRAINTS: unique across system (may be in pair with User_Defined_ID?)
-- OPTIONAL: can be generated automatically
PartitionID : AADLINTEGER 0 .. 255 applies to (virtual processor,process);
------------------------------------------------------------------
--- 4. AFDX Switch Properties
------------------------------------------------------------------
-- AFDX Switch Configuration Table
-- CONSTRAINTS: applicable to AFDX switches only
-- CONSTRAINTS: virtual links have to be bound to the switch
-- CONSTRAINTS: should contains entry for any virtual link bound to the switch
-- OPTIONAL: requires for configuration generation and detailed analysis
-- AADLv2.2 NOTE: could be a property of binding of VL to switch
-- AADLv2.2 NOTE: could be defined using a new built-in type (map: key->value)
VL_Route_Table : list of record (
vl : reference (virtual bus); -- MANDATORY: Virtual link
in_port : reference (bus access); -- OPTIONAL: can be evaluated from VL bindings
out_ports : list of reference (bus access); -- OPTIONAL: can be evaluated from VL bindings
jitter : TIME; -- MANDATORY: Maximum allowed Jitter
priority : enumeration (high, low); -- MANDATORY: priority
accountingPolicy : enumeration (byte, frame); -- MANDATORY: policy
sharedAccountId : aadlstring; -- OPTIONAL: specifying if this account is shared or not
) applies to (device,system);
-- Output Buffer Size for High/Low Priority VLs
-- CONSTRAINTS: applicable to ports of AFDX switches only
-- OPTIONAL: 1 by default
highPriorityQSize : aadlinteger 0 .. Max_Queue_Size => 1 applies to (bus access);
lowPriorityQSize : aadlinteger 0 .. Max_Queue_Size => 1 applies to (bus access);
-- An output port should not transmit frames that are older than "max delay".
-- The maximum delay parameter of a frame on a given port is defined as the maximum elapsed time between the two following events:
-- 1. Arrival of the last bit of a frame on the input port of a switch
-- 2. Exit of this last bit of the frame from the given output port of the switch
-- CONSTRAINTS: applicable to output bus access of AFDX switches only
-- MANDATORY: for each connected output port
-- Makes sense for bus accesses of AFDX switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in one place for the whole switch
maxDelay : inherit TIME applies to (bus access,device,system);
-- List of supported speeds
-- CONSTRAINTS: 10 MBpersec,100 MBpersec or 1000 MBpersec
-- OPTIONAL: mandatory to be able check consistency
-- Defined in section for end systems
-- Makes sense for bus accesses of end system and switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in device for all ports at once
-- Supported_Port_Speeds : inherit list of Data_Volume applies to (device,system,processor,bus access);
-- Speed of the physical port
-- CONSTRAINTS: should be in compliance with Supported_Port_Speeds of End System and Switch
-- CONSTRAINTS: must be defined at least on one side of each AFDX wire
-- OPTIONAL: see constraints above
-- Makes sense for bus accesses of end system and switch only (in other components for inheritance purposes only)
-- INHERITABLE to be defined in one place for the whole system
-- Defined in section for end systems
-- portSpeed : inherit Data_Volume applies to (device,system,bus access);
end AFDX_Properties2;
PACKAGE Software_Layer
Public
SYSTEM Software_Layer
END Software_Layer;
SYSTEM IMPLEMENTATION Software_Layer.i
SUBCOMPONENTS
P_1 : PROCESS P_1;
P_2 : PROCESS P_2;
P_3 : PROCESS P_3;
P_4 : PROCESS P_4;
CONNECTIONS
CQ_1_2: PORT P_1.qout1->P_2.qin1;
CS_1_2: PORT P_1.sout2->P_2.sin2;
C_2_3 : PORT P_2.qout1->P_3.qin1;
C_1_3 : PORT P_1.sout2->P_3.sin2;
C_1_4 : PORT P_1.sout2->P_4.sin2;
C_2_4 : PORT P_2.sout3->P_4.sin3;
END Software_Layer.i;
--- 2.1 Process P_1
PROCESS P_1
FEATURES
qout1 : OUT EVENT DATA PORT;
sout2 : OUT DATA PORT;
END P_1;
--- 2.2 Process P_2
PROCESS P_2
FEATURES
qin1 : IN EVENT DATA PORT;
qout1 : OUT EVENT DATA PORT;
sin2 : IN DATA PORT;
sout3 : OUT DATA PORT;
END P_2;
--- 2.3 Process P_3
PROCESS P_3
FEATURES
qin1 : IN EVENT DATA PORT;
sin2 : IN DATA PORT;
END P_3;
--- 2.4 Process P_4
PROCESS P_4
FEATURES
sin2 : IN DATA PORT;
sin3 : IN DATA PORT;
END P_4;
END Software_Layer;
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>ALSTOM-Ethernet-ntwk</name>
<comment></comment>
<projects>
<project>Plugin_Resources</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
<nature>org.osate.core.aadlnature</nature>
</natures>
</projectDescription>
package busses
public
bus ethernet
end ethernet;
end busses;
package processors
public
with busses;
processor processor_3p
features
p1: requires bus access busses::ethernet;
p2: requires bus access busses::ethernet;
p3: requires bus access busses::ethernet;
end processor_3p;
end processors;
package switches
public
with busses;
with AFDX_Properties;
device switch
properties
AFDX_Properties::maxDelay => 193 us;
end switch;
device switch_2p extends switch
features
p1: requires bus access busses::ethernet;
p2: requires bus access busses::ethernet;
end switch_2p;
device switch_3p extends switch_2p
features
p3: requires bus access busses::ethernet;
end switch_3p;
device switch_4p extends switch_3p
features
p4: requires bus access busses::ethernet;
end switch_4p;
end switches;
package SimpleExample
public
with AFDX_Properties;
system main
end main;
system implementation main.impl
subcomponents
flow_1 : virtual bus virtual_link;
properties
AFDX_Properties::portSpeed => 100 MBytesps;
AFDX_Properties::Lmin => 100 Mbyte applies to flow_1;
AFDX_Properties::Lmax => 100 Mbyte applies to flow_1;
AFDX_Properties::BAG => 32 ms applies to flow_1;
AFDX_Properties::Deadline => 54 ms applies to flow_1;
AFDX_Properties::priority => 2 applies to flow_1;
AFDX_Properties::jitter => 10 ms applies to flow_1;
end main.two_switches;
system implementation main.two_switches extends main.impl
subcomponents
HW : system HW_Platform.two_switches;
properties
-- path for flow 1
Actual_Connection_Binding => (reference (HW.end_system_1),
reference (HW.bus_1), reference(HW.switch_1),
reference(HW.bus_3), reference(HW.switch_2),
reference(HW.bus_2), reference (HW.end_system_2)
) applies to flow_1;
AFDX_Properties::portSpeed => 100 MBytesps;
AFDX_Properties::Lmin => 100 Mbyte applies to flow_1;
AFDX_Properties::Lmax => 100 Mbyte applies to flow_1;
AFDX_Properties::BAG => 32 ms applies to flow_1;
AFDX_Properties::Deadline => 54 ms applies to flow_1;
AFDX_Properties::maxDelay => 4 ms applies to HW.switch_1, HW.switch_2;
AFDX_Properties::priority => 2 applies to flow_1;
AFDX_Properties::jitter => 10 ms applies to flow_1;
end main.two_switches;
system implementation main.one_switch
subcomponents
flow_1 : virtual bus virtual_link;
HW : system HW_Platform.impl;
properties
-- path for flow 1
Actual_Connection_Binding => (reference (HW.end_system_1),
reference (HW.bus_1), reference(HW.switch_1),
reference(HW.bus_2), reference (HW.end_system_2)
) applies to flow_1;
AFDX_Properties::portSpeed => 100 MBytesps;
AFDX_Properties::Lmin => 100 Mbyte applies to flow_1;
AFDX_Properties::Lmax => 100 Mbyte applies to flow_1;
AFDX_Properties::BAG => 32 ms applies to flow_1;
AFDX_Properties::Deadline => 54 ms applies to flow_1;
AFDX_Properties::maxDelay => 4 ms applies to HW.switch_1;
AFDX_Properties::priority => 2 applies to flow_1;
AFDX_Properties::jitter => 10 ms applies to flow_1;
end main.one_switch;
virtual bus virtual_link
end virtual_link;
System HW_Platform
end HW_Platform;
system implementation HW_Platform.impl
subcomponents
end_system_1 : processor cpu;
end_system_2 : processor cpu;
switch_1 : device node_2p;
bus_1 : bus ethernet_wire;
bus_2 : bus ethernet_wire;
connections
cnx_processor_1 : bus access end_system_1.p -> bus_1;
cnx_processor_2: bus access end_system_2.p -> bus_2;
end HW_Platform.impl;
system implementation HW_Platform.one_switch extends HW_Platform.impl
connections
cnx_switch_1_1: bus access switch_1.p1 -> bus_1;
cnx_switch_1_2: bus access switch_1.p2 -> bus_2;
end HW_Platform.one_switch;
system implementation HW_Platform.two_switches extends HW_Platform.impl
subcomponents
switch_2: device node_2p;
bus_3: bus ethernet_wire;
connections
cnx_switch_1_1: bus access switch_1.p1 -> bus_1;
cnx_switch_1_3: bus access switch_1.p2 -> bus_3;
cnx_switch_2_3: bus access switch_2.p1 -> bus_3;
cnx_switch_2_2: bus access switch_2.p2 -> bus_2;
end HW_Platform.two_switches;
device node_1p
features
p1: requires bus access ethernet_wire;
end node_1p;
device node_2p extends node_1p
features
p2: requires bus access ethernet_wire;
end node_2p;
device node_3p extends node_2p
features
p3: requires bus access ethernet_wire;
end node_3p;
processor cpu
features
p: requires bus access ethernet_wire;
end cpu;
bus ethernet_wire
end ethernet_wire;
end SimpleExample;
\ No newline at end of file
package SwitchedEthernetNetworkExample
public
with AFDX_Properties;
system main
end main;
system implementation main.impl
subcomponents
flow_1 : virtual bus virtual_link;
flow_2 : virtual bus virtual_link;
flow_3 : virtual bus virtual_link;
HW : system HW_Platform.impl;
properties
-- path for flow 1
Actual_Connection_Binding => (reference (HW.end_system_1),
reference (HW.bus_1), reference(HW.switch_1),
reference(HW.bus_3), reference (HW.switch_2),
reference(HW.bus_4), reference (HW.end_system_2)
) applies to flow_1;
-- path for flow 2
Actual_Connection_Binding => (reference (HW.end_system_3),
reference (HW.bus_2), reference(HW.switch_1),
reference(HW.bus_3), reference (HW.switch_2),
reference(HW.bus_4), reference (HW.end_system_2)
) applies to flow_2;
-- path for flow 3
Actual_Connection_Binding => (reference (HW.end_system_4),
reference (HW.bus_6), reference (HW.switch_3),
reference(HW.bus_5), reference (HW.switch_2),
reference(HW.bus_4), reference (HW.end_system_2)
) applies to flow_3;
AFDX_Properties::portSpeed => 100 MBytesps;
AFDX_Properties::Lmin => 50 Bytes applies to flow_1, flow_2, flow_3;
AFDX_Properties::Lmax => 100 Bytes applies to flow_1, flow_2;
AFDX_Properties::Lmax => 80 Bytes applies to flow_3;
AFDX_Properties::BAG => 36 ms applies to flow_1, flow_2, flow_3;
AFDX_Properties::Deadline => 54 ms applies to flow_1,flow_2,flow_3;
AFDX_Properties::maxDelay => 4 ms applies to HW.switch_1,HW.switch_2,HW.switch_3;
AFDX_Properties::priority => 1 applies to flow_2,flow_3;
AFDX_Properties::priority => 2 applies to flow_1;
AFDX_Properties::jitter => 5 ms applies to flow_1,flow_2,flow_3;
end main.impl;
virtual bus virtual_link
end virtual_link;
System HW_Platform
end HW_Platform;
system implementation HW_Platform.impl
subcomponents
end_system_1 : processor cpu;
end_system_2 : processor cpu;
end_system_3 : processor cpu;
end_system_4 : processor cpu;
switch_1 : device node_3p;
switch_2 : device node_3p;
switch_3 : device node_2p;
bus_1 : bus ethernet_wire;
bus_2 : bus ethernet_wire;
bus_3 : bus ethernet_wire;
bus_4 : bus ethernet_wire;
bus_5 : bus ethernet_wire;
bus_6 : bus ethernet_wire;
connections
cnx_switch_1_1: bus access switch_1.p1 -> bus_1;
cnx_switch_2_1: bus access switch_2.p1 -> bus_3;
cnx_switch_2_2: bus access bus_4 -> switch_2.p2;
cnx_switch_3_1: bus access switch_3.p1 -> bus_5;
cnx_switch_1_2: bus access switch_1.p2 -> bus_2;
cnx_switch_1_3: bus access switch_1.p3 -> bus_3;
cnx_switch_2_3: bus access switch_2.p3 -> bus_5;
cnx_switch_3_2: bus access switch_3.p2 -> bus_6;
cnx_processor_1 : bus access end_system_1.p -> bus_1;
cnx_processor_2: bus access end_system_2.p -> bus_4;
cnx_processor_3: bus access end_system_3.p -> bus_2;
cnx_processor_4: bus access end_system_4.p -> bus_6;
end HW_Platform.impl;
device node_1p
features
p1: requires bus access ethernet_wire;
end node_1p;
device node_2p extends node_1p
features
p2: requires bus access ethernet_wire;
end node_2p;
device node_3p extends node_2p
features
p3: requires bus access ethernet_wire;
end node_3p;
processor cpu
features
p: requires bus access ethernet_wire;
end cpu;
bus ethernet_wire
end ethernet_wire;
end SwitchedEthernetNetworkExample;
\ No newline at end of file
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<classpathentry kind="con" path="org.eclipse.pde.core.requiredPlugins"/>
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<?xml version="1.0" encoding="UTF-8"?>
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<name>fr.tpt.mem4csd.sefa.examples</name>
<comment></comment>
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</projects>
<buildSpec>
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<natures>
<nature>org.eclipse.jdt.core.javanature</nature>
<nature>org.eclipse.pde.PluginNature</nature>
</natures>
</projectDescription>
Manifest-Version: 1.0
Bundle-ManifestVersion: 2
Bundle-Name: %providerName
Bundle-SymbolicName: fr.tpt.mem4csd.sefa.examples;singleton:=true
Bundle-Version: 0.0.1.qualifier
Export-Package: fr.tpt.mem4csd.sefa.examples
Require-Bundle: org.eclipse.ui;bundle-version="3.109.100",
fr.tpt.mem4csd.utils.eclipse.ui;bundle-version="0.0.1"
Bundle-ActivationPolicy: lazy
Bundle-Localization: plugin
source.. = src/
bin.includes = META-INF/,\
.,\
plugin.xml,\
icons/,\
examples_src/,\
plugin.properties
pluginName=SEFA Examples
providerName=https://mem4csd.telecom-paristech.fr/
exampleCategoryName=SEFA
exampleWizardName=SEFA Examples
exampleWizardDescr=Creates projects in the workspace for the SEFA plugin examples.
<?xml version="1.0" encoding="UTF-8"?>
<?eclipse version="3.4"?>
<plugin>
<extension
point="org.eclipse.ui.newWizards">
<category
id="fr.tpt.mem4csd.sefa.examples.category"
name="%exampleCategoryName"
parentCategory="org.eclipse.ui.Examples">
</category>
<wizard
canFinishEarly="true"
category="org.eclipse.ui.Examples/fr.tpt.mem4csd.sefa.examples.category"
class="fr.tpt.mem4csd.sefa.examples.SefaExamplesWizard"
hasPages="false"
icon="icons/Icon-trajectory.jpg"
id="fr.tpt.mem4csd.sefa.examples.SefaExamplesWizard"
name="%exampleWizardName"
project="true">
<description>
%exampleWizardDescr
</description>
</wizard>
</extension>
</plugin>
<?xml version="1.0" encoding="UTF-8"?>
<project
xsi:schemaLocation="http://maven.apache.org/POM/4.0.0 http://maven.apache.org/xsd/maven-4.0.0.xsd"
xmlns="http://maven.apache.org/POM/4.0.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<modelVersion>4.0.0</modelVersion>
<parent>
<groupId>sefa</groupId>
<artifactId>fr.tpt.mem4csd.sefa.build.main</artifactId>
<version>0.0.1-SNAPSHOT</version>
<relativePath>../fr.tpt.mem4csd.sefa.build.main/pom.xml</relativePath>
</parent>
<groupId>sefa</groupId>
<artifactId>fr.tpt.mem4csd.sefa.examples</artifactId>
<packaging>eclipse-plugin</packaging>
</project>
package fr.tpt.mem4csd.sefa.examples;
import fr.tpt.mem4csd.utils.eclipse.ui.AbstractExampleWizard;
/**
* Create the example projects.
*/
public class SefaExamplesWizard extends AbstractExampleWizard {
@Override
protected String[] getProjectNammes() {
return new String[]{"reference_example", "industrial_example" };
}
@Override
protected String getPluginId() {
return "fr.tpt.mem4csd.sefa.examples";
}
@Override
protected String getExamplesSourceDir() {
return "examples_src";
}
}
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>fr.tpt.mem4csd.sefa.feature</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.pde.FeatureBuilder</name>