Commit 32ea5c65 authored by Ludovic Apvrille's avatar Ludovic Apvrille

Merge branch 'vcd_test' into 'master'

vcd ok

See merge request !149
parents 4f102d5a e2e26135
......@@ -46,7 +46,8 @@
MemPoolNoDel<TMLTransaction> TMLTransaction::memPool(BLOCK_SIZE_TRANS);
TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0),_transactCoreNumber(0),_transVcdOutputState(END_IDLE_TRANS),
TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0),_transactCoreNumber(0),_transVcdOutputState(END_IDLE_TRANS),_endState(false),
/*_previousTransEndTime(0),*/
#ifdef PENALTIES_ENABLED
_idlePenalty(0), _taskSwitchingPenalty(0), //, _branchingPenalty(0),
#endif
......
......@@ -251,7 +251,11 @@ class TMLTransaction {
inline unsigned int getTransactCoreNumber() {return _transactCoreNumber;}
inline void setTransactCoreNumber(unsigned int num) {_transactCoreNumber=num;}
inline void setTransVcdOutPutState(vcdTransVisState n) {_transVcdOutputState=n;}
inline vcdTransVisState getTransVcdOutPutState() { return _transVcdOutputState;}
// inline void setPreviousTransEndTime(unsigned int n) {_previousTransEndTime=n;}
//inline unsigned int getPreviousTransEndTime() {return _previousTransEndTime;}
inline vcdTransVisState getTransVcdOutPutState() {return _transVcdOutputState;}
inline void setEndState (bool f) { _endState=f;}
inline bool getEndState () {return _endState;}
void toXML(std::ostringstream& glob, int deviceID, std::string deviceName) const;
......@@ -270,6 +274,10 @@ class TMLTransaction {
unsigned int _transactCoreNumber;
///State variable for the cpu VCD output
vcdTransVisState _transVcdOutputState;
//state of transaction for VCD output
bool _endState;
///previous end time for the cpu VCD output
// unsigned int _previousTransEndTime;
#ifdef PENALTIES_ENABLED
///Idle penalty
TMLTime _idlePenalty;
......
......@@ -539,16 +539,19 @@ void MultiCoreCPU::latencies2XML(std::ostringstream& glob, unsigned int id1, uns
void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
static bool _end=false;
//static bool _end=false;
std::cout<<"getNextSignalChangemulticore!!!---------"<<std::endl;
for( TransactionList::iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
std::cout<<"transaction core number is "<< (*i)->getTransactCoreNumber()<<std::endl;
std::cout<<"cycle time is "<< this->_cycleTime<<std::endl;
if( (*i)->getTransactCoreNumber() == this->_cycleTime ){
_posTrasactListVCD= i;
std::cout<<"cpu core number "<< oSigData->_coreNumberVcd<<std::endl;
if( (*i)->getTransactCoreNumber() == oSigData->_coreNumberVcd){
std::cout<<"bingo!!"<<(*i)->toShortString()<<std::endl;
//if(_transactList.end()==0) std::cout<<"what???"<<std::endl;
//std::cout<<(*_transactList.end())->toShortString()<<std::endl;
if (iInit){
//_posTrasactListVCD= i;
_posTrasactListVCD= i;
_previousTransEndTime=0;
(*i)->setTransVcdOutPutState(END_IDLE_TRANS);
std::cout<<"init"<<std::endl;
......@@ -560,37 +563,56 @@ void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
return;
}
}
if (_end==true || _posTrasactListVCD == _transactList.end()){
if ((*i)->getEndState() == true){
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
//oSigChange=outp.str();
//oNoMoreTrans=true;
//return _previousTransEndTime;
std::cout<<"end transact"<<std::endl;
new (oSigData) SignalChangeData(END_IDLE_TRANS, _previousTransEndTime, this);
this->_cycleTime++;
_end=false;
std::cout<<"end trans"<<(*i)->getEndTime()<<std::endl;
new (oSigData) SignalChangeData(END_IDLE_TRANS, (*i)->getEndTime(), this);
break;
}else{
//_posTrasactListVCD = i;
_posTrasactListVCD = i;
TMLTransaction* aCurrTrans=*_posTrasactListVCD;
switch (aCurrTrans->getTransVcdOutPutState()){
case END_TASK_TRANS:
case END_TASK_TRANS:
std::cout<<"END_TASK_CPU"<<std::endl;
do{
std::cout<<"1111"<<std::endl;
_previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
_posTrasactListVCD++;
std::cout<<"2222"<<std::endl;
while(_posTrasactListVCD != _transactList.end()){
if((*_posTrasactListVCD)->getTransactCoreNumber() == oSigData->_coreNumberVcd)
break;
else
_posTrasactListVCD++;
}
std::cout<<"3333"<<std::endl;
}while (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTimeOperation()==_previousTransEndTime);
// std::cout<<"4444"<<std::endl;
if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()==_previousTransEndTime){
//outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
aCurrTrans->setTransVcdOutPutState(END_PENALTY_TRANS);
std::cout<<"!!!~~~"<<(*_posTrasactListVCD)->toShortString()<<std::endl;
(*_posTrasactListVCD)->setTransVcdOutPutState(END_PENALTY_TRANS);
std::cout<<"almost!!!"<<std::endl;
new (oSigData) SignalChangeData(END_PENALTY_TRANS, _previousTransEndTime, this);
}else{
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
aCurrTrans->setTransVcdOutPutState(END_IDLE_TRANS);
//if (_posTrasactListVCD == _transactList.end()) oNoMoreTrans=true;
std::cout<<"what is previous time "<<_previousTransEndTime<<std::endl;
std::cout<<"and this??"<<oSigData->_time<<std::endl;
// if(oSigData->_time != _previousTransEndTime) new (oSigData) SignalChangeData(END_PENALTY_TRANS, _previousTransEndTime, this);
new (oSigData) SignalChangeData(END_IDLE_TRANS, _previousTransEndTime, this);
_end=true;
//_posTrasactListVCD = _transactList.end();
//std::cout<<(*_posTrasactListVCD)->toShortString()<<std::endl;
if (_posTrasactListVCD == _transactList.end()) {aCurrTrans->setEndState(true);std::cout<<"hahaha"<<std::endl;}
}
_transactList.erase(i);
//oSigChange=outp.str();
//return _previousTransEndTime;
// this->_cycleTime++;
......@@ -602,6 +624,7 @@ void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//oSigChange=outp.str();
aCurrTrans->setTransVcdOutPutState(END_TASK_TRANS);
//return aCurrTrans->getStartTimeOperation();
std::cout<<"time in penalty is "<< aCurrTrans->getStartTimeOperation()<<std::endl;
new (oSigData) SignalChangeData(END_TASK_TRANS, aCurrTrans->getStartTimeOperation(), this);
break;
case END_IDLE_TRANS:
......@@ -618,8 +641,9 @@ void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//oSigChange=outp.str();
//return aCurrTrans->getStartTime();
break;
}
}
}
break;
}
}
......
......@@ -459,7 +459,9 @@ void SingleCoreCPU::latencies2XML(std::ostringstream& glob, unsigned int id1, un
void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
if (iInit){
_posTrasactListVCD=_transactList.begin();
std::cout<<"init "<<(*_posTrasactListVCD)->toShortString()<<std::endl;
_previousTransEndTime=0;
_vcdOutputState = END_IDLE_CPU;
if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()!=0){
......@@ -469,12 +471,15 @@ void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
}
if (_posTrasactListVCD == _transactList.end()){
std::cout<<"end trans"<<std::endl;
new (oSigData) SignalChangeData(END_IDLE_CPU, _previousTransEndTime, this);
}
else{
TMLTransaction* aCurrTrans=*_posTrasactListVCD;
std::cout<<"current trans is "<<aCurrTrans->toShortString()<<std::endl;
switch (_vcdOutputState){
case END_TASK_CPU:
std::cout<<"END_TASK_CPU"<<std::endl;
do{
_previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
_posTrasactListVCD++;
......@@ -482,6 +487,7 @@ void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()==_previousTransEndTime){
//outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
_vcdOutputState=END_PENALTY_CPU;
std::cout<<"why???"<<std::endl;
new (oSigData) SignalChangeData(END_PENALTY_CPU, _previousTransEndTime, this);
}else{
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
......@@ -493,6 +499,7 @@ void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//return _previousTransEndTime;
break;
case END_PENALTY_CPU:
std::cout<<"END_PENALTY_CPU"<<std::endl;
//outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
//oSigChange=outp.str();
_vcdOutputState=END_TASK_CPU;
......@@ -500,6 +507,7 @@ void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
new (oSigData) SignalChangeData(END_TASK_CPU, aCurrTrans->getStartTimeOperation(), this);
break;
case END_IDLE_CPU:
std::cout<<"END_IDLE_CPU"<<std::endl;
if (aCurrTrans->getPenalties()==0){
//outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
_vcdOutputState=END_TASK_CPU;
......@@ -513,6 +521,7 @@ void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//return aCurrTrans->getStartTime();
break;
}
}
//return 0;
}
......
......@@ -689,7 +689,7 @@ public:
SignalChangeData(unsigned int iSigChange, TMLTime iTime, TraceableDevice* iDevice):_sigChange(iSigChange),_time(iTime),_device(iDevice){
//std::cout << _sigChange << " " << _time << " " << _device << " " << " constructor***\n";
}
SignalChangeData():_sigChange(0),_time(0),_device(0){
SignalChangeData():_sigChange(0),_time(0),_device(0),_coreNumberVcd(0){
}
///String representation of the signal change in VCD format
//std::string _sigChange;
......@@ -698,6 +698,8 @@ public:
TMLTime _time;
///Pointer to the device the signal belongs to
TraceableDevice* _device;
///for cpu,the correspond core number
unsigned int _coreNumberVcd;
};
///Function object for the comparison of the runnable time of two transaction
......
......@@ -392,7 +392,7 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
if (myfile.is_open()){
//std::cout << "File is open" << std::endl;
SignalChangeQueue aQueue;
SignalChangeQueue aQueueCPU;
//std::queue<SignalChangeData*> aQueue;
//std::string aSigString;
//bool aNoMoreTrans;
//TraceableDevice* actDevice;
......@@ -402,7 +402,7 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
myfile << "$date\n" << asctime(aTimeinfo) << "$end\n\n$version\nDaniel's TML simulator\n$end\n\n";
myfile << "$timescale\n5 ns\n$end\n\n$scope module Simulation $end\n";
//std::cout << "Before 1st loop" << std::endl;
for (TraceableDeviceList::const_iterator i=_simComp->getVCDList().begin(); i!= _simComp->getVCDList().end(); ++i){
//TraceableDevice* a=*i;
// a->streamBenchmarks(std::cout);
......@@ -413,53 +413,12 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
if ((*i)->toShortString().substr(0,3) == "cpu"){
for(unsigned int j = 0; j < (dynamic_cast<CPU*>(*i))->getAmoutOfCore(); j++) {
myfile << "$var wire 1 " << (*i)->toShortString() << " " << (*i)->toString() <<"_Core"<<(j+1)<< " $end\n";
myfile << "$var wire 1 " << (*i)->toShortString() << "_core" << j << " " << (*i)->toString() <<"_Core"<<j<< " $end\n";
aTopElement = new SignalChangeData();
aTopElement->_coreNumberVcd=j;
(*i)->getNextSignalChange(true, aTopElement);
aQueueCPU.push(aTopElement);
myfile << "$var integer 32 clk Clock $end\n";
myfile << "$upscope $end\n$enddefinitions $end\n\n";
while (!aQueueCPU.empty()){
//static unsigned int count = 0;
std::cout<<"this is CPU queue"<<std::endl;
aTopElement=aQueueCPU.top();
std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<<std::endl;
while (aNextClockEvent < aTopElement->_time){
myfile << "#" << aNextClockEvent << "\nr" << aNextClockEvent << " clk\n";
aNextClockEvent+=CLOCK_INC;
}
if (aCurrTime!=aTopElement->_time){
aCurrTime=aTopElement->_time;
myfile << "#" << aCurrTime << "\n";
}
if (aNextClockEvent == aTopElement->_time){
myfile << "b" << vcdTimeConvert(aNextClockEvent) << " clk\n";
aNextClockEvent+=CLOCK_INC;
}
//myfile << aTopElement->_sigChange << "\n";
myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "\n";
aQueueCPU.pop();
TMLTime aTime = aTopElement->_time;
//std::cout<<"lets get next signal : )"<<std::endl;
//if (aTopElement->_device->toShortString().substr(0,3) == "cpu")
// std::cout<<"!!!!!"<<(dynamic_cast<CPU*>(aTopElement->_device))->getCycleTime()<<std::endl;
std::cout<<"The cycle is cpu is ~~~!!"<<dynamic_cast<CPU*>(aTopElement->_device)->getCycleTime()<<std::endl;
aTopElement->_device->getNextSignalChange(false, aTopElement);
//dynamic_cast<CPU*>(aTopElement->_device)->setCycleTime((++count)% (dynamic_cast<CPU*>(aTopElement->_device)->getAmoutOfCore()));
std::cout<<"aTime is "<<aTime<<std::endl;
std::cout<<"top element time is "<<aTopElement->_time<<std::endl;
if (aTopElement->_time == aTime){
delete aTopElement;
std::cout<<"delete"<<std::endl;
}
else{
aQueueCPU.push(aTopElement);
std::cout<<"no delete"<<std::endl;
}
}
aQueue.push(aTopElement);
// (dynamic_cast<CPU*>(*i))->setCycleTime( (dynamic_cast<CPU*>(*i))->getCycleTime()+1);
}
}
......@@ -478,39 +437,45 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
//if sucess, make it as a fonction !!!! change
/* for (TraceableDeviceList::const_iterator i=_simComp->getVCDList().begin(); i!= _simComp->getVCDList().end(); ++i){
for (TraceableDeviceList::const_iterator i=_simComp->getVCDList().begin(); i!= _simComp->getVCDList().end(); ++i){
if ((*i)->toShortString().substr(0,3) == "cpu"){
for(unsigned int j = 0; j < (dynamic_cast<CPU*>(*i))->getAmoutOfCore(); j++) {
(dynamic_cast<CPU*>(*i))->setCycleTime(0);
}
}
}*/
}
myfile << "$var integer 32 clk Clock $end\n";
myfile << "$upscope $end\n$enddefinitions $end\n\n";
//TMLTime aTimeCPU=0;
while (!aQueue.empty()){
std::cout<<"this is queue"<<std::endl;
aTopElement=aQueue.top();
std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<<std::endl;
if( aTopElement->_device->toShortString().substr(0,3) == "cpu")
std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<< "_core" << aTopElement->_coreNumberVcd<<std::endl;
else
std::cout<<"the member of queue is "<<aTopElement->_device->toShortString() <<std::endl;
while (aNextClockEvent < aTopElement->_time){
myfile << "#" << aNextClockEvent << "\nr" << aNextClockEvent << " clk\n";
aNextClockEvent+=CLOCK_INC;
//std::cout<<"aaaa"<<std::endl;
}
if (aCurrTime!=aTopElement->_time){
aCurrTime=aTopElement->_time;
//std::cout<<"bbbbb"<<std::endl;
myfile << "#" << aCurrTime << "\n";
}
if (aNextClockEvent == aTopElement->_time){
myfile << "b" << vcdTimeConvert(aNextClockEvent) << " clk\n";
//std::cout<<"ccccc"<<std::endl;
aNextClockEvent+=CLOCK_INC;
}
//myfile << aTopElement->_sigChange << "\n";
myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "\n";
if( aTopElement->_device->toShortString().substr(0,3) == "cpu")
myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "_core" << aTopElement->_coreNumberVcd << "\n";
else myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "\n";
aQueue.pop();
TMLTime aTime = aTopElement->_time;
aTopElement->_device->getNextSignalChange(false, aTopElement);
......@@ -525,6 +490,7 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
std::cout<<"no delete"<<std::endl;
}
}
//actDevice=aTopElement->_device;
//if (actDevice!=0) aTime = actDevice->getNextSignalChange(false, aSigString, aNoMoreTrans);
......
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