Commit 7655a1e2 authored by Siyuan Niu's avatar Siyuan Niu

name for fpga and task is ok

parent 258eeb03
......@@ -46,7 +46,7 @@
MemPoolNoDel<TMLTransaction> TMLTransaction::memPool(BLOCK_SIZE_TRANS);
TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0), _transactCoreNumber(0), _transFpgaNumber(0), _transVcdOutputState(END_IDLE_TRANS),_endState(false),
TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0), _transactCoreNumber(0), _transVcdOutputState(END_IDLE_TRANS),_endState(false),
/*_previousTransEndTime(0),*/
#ifdef PENALTIES_ENABLED
_idlePenalty(0), _taskSwitchingPenalty(0), //, _branchingPenalty(0),
......
......@@ -251,8 +251,6 @@ class TMLTransaction {
inline unsigned int getTransactCoreNumber() {return _transactCoreNumber;}
inline void setTransactCoreNumber(unsigned int num) {_transactCoreNumber=num;}
inline void setTransVcdOutPutState(vcdTransVisState n) {_transVcdOutputState=n;}
inline void setTransFpgaNumber(unsigned int num) { _transFpgaNumber=num;}
inline unsigned int getTransFpgaNumber() { return _transFpgaNumber;}
// inline void setPreviousTransEndTime(unsigned int n) {_previousTransEndTime=n;}
//inline unsigned int getPreviousTransEndTime() {return _previousTransEndTime;}
inline vcdTransVisState getTransVcdOutPutState() {return _transVcdOutputState;}
......@@ -274,8 +272,6 @@ class TMLTransaction {
TMLCommand* _command;
///Core number of the transaction
unsigned int _transactCoreNumber;
///Number of trans for FPGA
unsigned int _transFpgaNumber;
///State variable for the cpu VCD output
vcdTransVisState _transVcdOutputState;
//state of transaction for VCD output
......
......@@ -61,7 +61,7 @@ FPGA::FPGA( ID iID,
,_cyclesBeforeIdle(iCyclesBeforeIdle)
,_cyclesPerExeci(iCyclesPerExeci)
,_cyclesPerExecc(iCyclesPerExecc)
,_transNumber(1)
{}
......@@ -222,7 +222,6 @@ std::cout<<"fpga addTransaction"<<std::endl;
if (aFinish){
//std::cout<<"I am in finish!!!"<<std::endl;
_nextTransaction->setTransFpgaNumber(_transNumber++);
_endSchedule=0;
_simulatedTime=max(_simulatedTime,_endSchedule);
_overallTransNo++; //NEW!!!!!!!!
......@@ -281,9 +280,9 @@ void FPGA::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
std::cout<<"getNextSignalChangemulticore!!!---------"<<std::endl;
for( TransactionList::iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
std::cout<<"transaction core number is "<< (*i)->getTransFpgaNumber()<<std::endl;
std::cout<<"cpu core number "<< oSigData->_transNumberVcd<<std::endl;
if( (*i)->getTransFpgaNumber() == oSigData->_transNumberVcd){
// std::cout<<"transaction core number is "<< (*i)->getTransFpgaNumber()<<std::endl;
// std::cout<<"cpu core number "<< oSigData->_transNumberVcd<<std::endl;
if( (*i)-> getCommand()->getTask() == oSigData->_taskFPGA){
std::cout<<"bingo!!"<<(*i)->toShortString()<<std::endl;
......
......@@ -178,8 +178,7 @@ protected:
///Idle time which elapses before entering idle mode
TMLTime _timeBeforeIdle;
///Time needed to switch into idle mode
TMLTime _changeIdleModeTime;
unsigned int _transNumber;
TMLTime _changeIdleModeTime;
///State variable for the VCD output
vcdFPGAVisState _vcdOutputState;
};
......
......@@ -728,7 +728,7 @@ public:
SignalChangeData(unsigned int iSigChange, TMLTime iTime, TraceableDevice* iDevice):_sigChange(iSigChange),_time(iTime),_device(iDevice){
//std::cout << _sigChange << " " << _time << " " << _device << " " << " constructor***\n";
}
SignalChangeData():_sigChange(0),_time(0),_device(0),_coreNumberVcd(0),_transNumberVcd(0){
SignalChangeData():_sigChange(0),_time(0),_device(0),_coreNumberVcd(0),_taskFPGA(0){
}
///String representation of the signal change in VCD format
//std::string _sigChange;
......@@ -739,7 +739,7 @@ public:
TraceableDevice* _device;
///for cpu,the correspond core number
unsigned int _coreNumberVcd;
unsigned int _transNumberVcd;
TMLTask* _taskFPGA;
};
///Function object for the comparison of the runnable time of two transaction
......
......@@ -505,16 +505,13 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
}
}
else if((*i)->toShortString().substr(0,4) == "fpga"){
unsigned int n = 1;
for(TaskList::const_iterator j = _simComp->getTaskList().begin(); j != _simComp->getTaskList().end(); j++){
std::cout<<"haha in"<<std::endl;
std::cout<<"name of fpga is : "<< (*i)->toShortString() << "_T" << n <<std::endl;
myfile << "$var wire 1 " << (*i)->toShortString() << "_T" << n << " " << (*i)->toString() << "_T" << n << " $end\n";
std::cout<<"name of fpga is : "<< (*i)->toShortString() << "_" << (*j)->toString() << std::endl;
myfile << "$var wire 1 " << (*i)->toShortString() << "_" << (*j)->toString() << " " << (*i)->toString() << "_" << (*j)->toString() << " $end\n";
aTopElement = new SignalChangeData();
aTopElement->_transNumberVcd=n;
aTopElement->_taskFPGA=(*j);
(*i)->getNextSignalChange(true, aTopElement);
aQueue.push(aTopElement);
n++;
}
}
else{
......@@ -542,7 +539,7 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
if( aTopElement->_device->toShortString().substr(0,3) == "cpu")
std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<< "_core" << aTopElement->_coreNumberVcd<<std::endl;
else if( aTopElement->_device->toShortString().substr(0,4) == "fpga")
std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<< "_T" << aTopElement->_transNumberVcd<<std::endl;
std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<< "_" << aTopElement->_taskFPGA->toString()<<std::endl;
else
std::cout<<"the member of queue is "<<aTopElement->_device->toShortString() <<std::endl;
......@@ -567,7 +564,7 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "_core" << aTopElement->_coreNumberVcd << "\n";
else if( aTopElement->_device->toShortString().substr(0,4) == "fpga")
myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "_T" << aTopElement->_transNumberVcd << "\n";
myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "_" << aTopElement->_taskFPGA->toString() << "\n";
else if( aTopElement->_device->toShortString().substr(0,2) == "ta" )
myfile <<"b"<< vcdTaskValConvert(aTopElement->_sigChange) <<" "<< aTopElement->_device->toShortString() << "\n";
......
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