Commit a311edcb authored by Ludovic Apvrille's avatar Ludovic Apvrille

Merge branch 'fpga_change' into 'master'

Fpga change

See merge request !161
parents b57d21a7 0be8fa3e
......@@ -24,7 +24,7 @@ OS := $(shell uname)
MODULE = run
include Makefile.src
SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/RRPrioScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/FPGA.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/RRPrioScheduler.cpp arch/OrderScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
SRCS_base_DIR = src_simulator
SRCS_generated = .
......
......@@ -358,7 +358,7 @@ unsigned int TMLTask::getState() const{
}
TMLTransaction* TMLTask::getNextTransaction(TMLTime iEndSchedule) const{
//std::cout << "Task::getNextTransaction\n";
std::cout<<"TMLTask get next trans"<<std::endl;
return (_currCommand==0)?0:_currCommand->getCurrTransaction();
//return (_currCommand==0 || _isScheduled)?0:_currCommand->getCurrTransaction();
}
......
This diff is collapsed.
......@@ -71,9 +71,6 @@ public:
\param iID ID of the device
\param iName Name of the device
\param iScheduler Pointer to the scheduler object
\param iTimePerCycle 1/Processor frequency
\param iMapCapacity Pointer to the overall mapping capacity ????
\param iMapPenalty Pointer to the mapping penalty ????
\param iReconfigTime reconfiguration time
\param iChangeIdleModeCycles Cycles needed to switch into indle mode
\param iCyclesBeforeIdle Pointer to the max consecutive cycles before idle in cycle
......@@ -81,7 +78,7 @@ public:
\param iCyclesPerExecc Cycles needed to execute one EXECC unit
*/
FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iTimePerCycle, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
///Destructor
virtual ~FPGA();
///Determines the next FPGA transaction to be executed
......@@ -130,10 +127,18 @@ public:
_taskList.push_back(iTask);
if (_scheduler!=0) _scheduler->addWorkloadSource(iTask);
}
inline void setTransNumber(unsigned int num) { _transNumber=num;}
inline unsigned int getTransNumber() { return _transNumber;}
double averageLoad (TMLTask* currTask) const;
void drawPieChart(std::ofstream& myfile) const;
void showPieChart(std::ofstream& myfile) const;
void schedule2HTML(std::ofstream& myfile) const;
inline const TaskList& getTaskList() const{return _taskList;}
inline void setHtmlCurrTask(TMLTask *t) { _htmlCurrTask=t;}
protected:
///List of all tasks running on the FPGA
TaskList _taskList;
TMLTask* _htmlCurrTask;
/**
\param iTime Indicates at what time the transaction should be truncated
*/
......@@ -142,12 +147,11 @@ protected:
/**
\param iTimeSlice FPGA Time slice granted by the scheduler
*/
void calcStartTimeLength(TMLTime iTimeSlice);
///1/Processor frequency
TMLTime _timePerCycle;
void calcStartTimeLength();
TMLTime _reconfigTime;
///Determines the correct bus master of this CPU connected to the same bus as bus master iDummy
/**
\param iDummy Dummy Bus Master
......@@ -159,22 +163,25 @@ protected:
TMLTransaction* _lastTransaction;
///List of bus masters
BusMasterList _busMasterList;
#ifdef PENALTIES_ENABLED
///Cycles needed to switch to idle mode
unsigned int _changeIdleModeCycles;
///Idle cycles which elapse before entering idle mode
unsigned int _cyclesBeforeIdle;
#endif
///Cycles needed to execute one execi unit
unsigned int _cyclesPerExeci;
unsigned int _cyclesPerExecc;
///Time needed to execute one execi unit
float _timePerExeci;
#ifdef PENALTIES_ENABLED
///Idle time which elapses before entering idle mode
TMLTime _timeBeforeIdle;
///Time needed to switch into idle mode
TMLTime _changeIdleModeTime;
#endif
unsigned int _transNumber;
///State variable for the VCD output
vcdFPGAVisState _vcdOutputState;
};
......
/*Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Niu Siyuan,
Ludovic Apvrille, Renaud Pacalet
*
* ludovic.apvrille AT telecom-paristech.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*
*/
#include<OrderScheduler.h>
#include <TMLTransaction.h>
OrderScheduler::OrderScheduler(const std::string& iName, Priority iPrio): WorkloadSource(iPrio), _name(iName), _nextTransaction(0) {
}
OrderScheduler::OrderScheduler(const std::string& iName, Priority iPrio, WorkloadSource** aSourceArray, unsigned int iNbOfSources): WorkloadSource(iPrio, aSourceArray, iNbOfSources), _name(iName), _nextTransaction(0), _lastSource(0) {
}
TMLTime OrderScheduler::schedule(TMLTime iEndSchedule){
TaskList::iterator i;
TMLTransaction *aMarkerPast=0, *aMarkerFuture=0,*aTempTrans;
TMLTime aTransTimeFuture=-1,aRunnableTime;
WorkloadSource *aSourcePast=0, *aSourceFuture=0; //NEW
for(WorkloadList::iterator i=_workloadList.begin(); i != _workloadList.end(); ++i){
(*i)->schedule(iEndSchedule);
aTempTrans=(*i)->getNextTransaction(iEndSchedule);
if (aTempTrans!=0 && aTempTrans->getVirtualLength()!=0){
aRunnableTime=aTempTrans->getRunnableTime();
if (aRunnableTime<=iEndSchedule){
//Past
aMarkerPast=aTempTrans;
aSourcePast=*i; //NEW
}else{
//Future
aTransTimeFuture=aRunnableTime;
aMarkerFuture=aTempTrans;
aSourceFuture=*i; //NEW
}
}
}
if (aMarkerPast==0){
_nextTransaction=aMarkerFuture;
_lastSource=aSourceFuture; //NEW
}else{
_nextTransaction=aMarkerPast;
_lastSource=aSourcePast; //NEW
}
return 0;
}
OrderScheduler::~OrderScheduler(){
std::cout << _name << ": Scheduler deleted\n";
}
void OrderScheduler::reset(){
WorkloadSource::reset();
_nextTransaction=0;
}
/*Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Niu Siyuan,
Ludovic Apvrille, Renaud Pacalet
*
* ludovic.apvrille AT telecom-paristech.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*
*/
#ifndef PrioSchedulerH
#define PrioSchedulerH
#include <WorkloadSource.h>
class TMLTransaction;
///Fixed priority based scheduler
class OrderScheduler: public WorkloadSource{
public:
///Constructor
/**
\param iName Name of the scheduler
\param iPrio Priority of the scheduler
*/
OrderScheduler(const std::string& iName, Priority iPrio);
///Constructor
/**
\param iName Name of the scheduler
\param iPrio Priority of the scheduler
\param aSourceArray Array of pointers to workload ressources from which transactions may be received
\param iNbOfSources Length of the array
*/
OrderScheduler(const std::string& iName, Priority iPrio, WorkloadSource** aSourceArray, unsigned int iNbOfSources);
~OrderScheduler();
TMLTime schedule(TMLTime iEndSchedule);
inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {return _nextTransaction;}
inline std::string toString() const {return _name;}
void reset();
//void transWasScheduled(SchedulableDevice* iDevice);
protected:
///Name of the scheduler
std::string _name;
///Next transaction to be executed
TMLTransaction* _nextTransaction;
///Last workload source to which ressource access was granted
WorkloadSource* _lastSource;
};
#endif
......@@ -123,7 +123,9 @@ TMLTime RRScheduler::schedule(TMLTime iEndSchedule){
// _nextTransaction->setLength(min(_nextTransaction->getOperationLength(), _timeSlice-_elapsedTime));
//}
//std::cout << "End schedule\n" ;
return _timeSlice-_elapsedTime;
}
//TMLTransaction* RRScheduler::getNextTransaction(TMLTime iEndSchedule) const{
......
......@@ -69,7 +69,7 @@ public:
///Destructor
~RRScheduler();
TMLTime schedule(TMLTime iEndSchedule);
inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {return _nextTransaction;}
inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {if(_nextTransaction) std::cout<<"rr next trans"<<std::endl;return _nextTransaction;}
void reset();
std::istream& readObject(std::istream &is);
std::ostream& writeObject(std::ostream &os);
......
......@@ -191,13 +191,14 @@ std::string SchedulableDevice::determineHTMLCellClass( std::map<TMLTask*, std::
double SchedulableDevice::averageLoad() const{
std::cout<<"average load"<<std::endl;
double _averageLoad=0;
TMLTime _maxEndTime=0;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
TMLTime _endTime= (*i)->getEndTime();
_maxEndTime=max(_maxEndTime,_endTime);
}
std::cout<<"max end time is "<<_maxEndTime<<std::endl;
// std::cout<<"max end time is "<<_maxEndTime<<std::endl;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
_averageLoad += (*i)->getEndTime() - (*i)->getStartTime();
......
......@@ -311,12 +311,14 @@ std::cout<<"addTransaction"<<std::endl;
void SingleCoreCPU::schedule(){
//std::cout <<"Hello\n";
std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
// std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
std::cout<<"CPU schedule"<<std::endl;
TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
//_schedulingNeeded=false; 05/05/11
//std::cout << "1\n";
TMLTransaction* aOldTransaction = _nextTransaction;
_nextTransaction=_scheduler->getNextTransaction(_endSchedule);
if(_nextTransaction) std::cout<<"next trans is "<<_nextTransaction->toShortString()<<std::endl;
else std::cout<<"next trans is 0"<<std::endl;
//std::cout << "2\n";
//_scheduler->transWasScheduled(this); //NEW 05/05/11
......
......@@ -71,6 +71,7 @@ Ludovic Apvrille, Renaud Pacalet
#endif
class CPU;
class FPGA;
class TMLTransaction;
class TMLCommand;
class TMLTask;
......
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