Commit f1bda6a9 authored by apvrille's avatar apvrille

Update on simulator:revert to working version

parent b39798b9
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......@@ -71,6 +71,9 @@ public:
\param iID ID of the device
\param iName Name of the device
\param iScheduler Pointer to the scheduler object
\param iTimePerCycle 1/Processor frequency
\param iMapCapacity Pointer to the overall mapping capacity ????
\param iMapPenalty Pointer to the mapping penalty ????
\param iReconfigTime reconfiguration time
\param iChangeIdleModeCycles Cycles needed to switch into indle mode
\param iCyclesBeforeIdle Pointer to the max consecutive cycles before idle in cycle
......@@ -78,7 +81,7 @@ public:
\param iCyclesPerExecc Cycles needed to execute one EXECC unit
*/
FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iTimePerCycle, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
///Destructor
virtual ~FPGA();
///Determines the next FPGA transaction to be executed
......@@ -127,18 +130,10 @@ public:
_taskList.push_back(iTask);
if (_scheduler!=0) _scheduler->addWorkloadSource(iTask);
}
inline void setTransNumber(unsigned int num) { _transNumber=num;}
inline unsigned int getTransNumber() { return _transNumber;}
double averageLoad (TMLTask* currTask) const;
void drawPieChart(std::ofstream& myfile) const;
void showPieChart(std::ofstream& myfile) const;
void schedule2HTML(std::ofstream& myfile) const;
inline const TaskList& getTaskList() const{return _taskList;}
inline void setHtmlCurrTask(TMLTask *t) { _htmlCurrTask=t;}
protected:
///List of all tasks running on the FPGA
TaskList _taskList;
TMLTask* _htmlCurrTask;
/**
\param iTime Indicates at what time the transaction should be truncated
*/
......@@ -147,11 +142,12 @@ protected:
/**
\param iTimeSlice FPGA Time slice granted by the scheduler
*/
void calcStartTimeLength();
void calcStartTimeLength(TMLTime iTimeSlice);
///1/Processor frequency
TMLTime _timePerCycle;
TMLTime _reconfigTime;
///Determines the correct bus master of this CPU connected to the same bus as bus master iDummy
/**
\param iDummy Dummy Bus Master
......@@ -163,25 +159,22 @@ protected:
TMLTransaction* _lastTransaction;
///List of bus masters
BusMasterList _busMasterList;
#ifdef PENALTIES_ENABLED
///Cycles needed to switch to idle mode
unsigned int _changeIdleModeCycles;
///Idle cycles which elapse before entering idle mode
unsigned int _cyclesBeforeIdle;
#endif
///Cycles needed to execute one execi unit
unsigned int _cyclesPerExeci;
unsigned int _cyclesPerExecc;
///Time needed to execute one execi unit
float _timePerExeci;
#ifdef PENALTIES_ENABLED
///Idle time which elapses before entering idle mode
TMLTime _timeBeforeIdle;
///Time needed to switch into idle mode
TMLTime _changeIdleModeTime;
unsigned int _transNumber;
#endif
///State variable for the VCD output
vcdFPGAVisState _vcdOutputState;
};
......
......@@ -123,9 +123,7 @@ TMLTime RRScheduler::schedule(TMLTime iEndSchedule){
// _nextTransaction->setLength(min(_nextTransaction->getOperationLength(), _timeSlice-_elapsedTime));
//}
//std::cout << "End schedule\n" ;
return _timeSlice-_elapsedTime;
}
//TMLTransaction* RRScheduler::getNextTransaction(TMLTime iEndSchedule) const{
......
......@@ -69,7 +69,7 @@ public:
///Destructor
~RRScheduler();
TMLTime schedule(TMLTime iEndSchedule);
inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {if(_nextTransaction) std::cout<<"rr next trans"<<std::endl;return _nextTransaction;}
inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {return _nextTransaction;}
void reset();
std::istream& readObject(std::istream &is);
std::ostream& writeObject(std::ostream &os);
......
......@@ -191,14 +191,13 @@ std::string SchedulableDevice::determineHTMLCellClass( std::map<TMLTask*, std::
double SchedulableDevice::averageLoad() const{
std::cout<<"average load"<<std::endl;
double _averageLoad=0;
TMLTime _maxEndTime=0;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
TMLTime _endTime= (*i)->getEndTime();
_maxEndTime=max(_maxEndTime,_endTime);
}
// std::cout<<"max end time is "<<_maxEndTime<<std::endl;
std::cout<<"max end time is "<<_maxEndTime<<std::endl;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
_averageLoad += (*i)->getEndTime() - (*i)->getStartTime();
......
......@@ -311,14 +311,12 @@ std::cout<<"addTransaction"<<std::endl;
void SingleCoreCPU::schedule(){
//std::cout <<"Hello\n";
// std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
std::cout<<"CPU schedule"<<std::endl;
std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
//_schedulingNeeded=false; 05/05/11
//std::cout << "1\n";
TMLTransaction* aOldTransaction = _nextTransaction;
_nextTransaction=_scheduler->getNextTransaction(_endSchedule);
if(_nextTransaction) std::cout<<"next trans is "<<_nextTransaction->toShortString()<<std::endl;
else std::cout<<"next trans is 0"<<std::endl;
//std::cout << "2\n";
//_scheduler->transWasScheduled(this); //NEW 05/05/11
......
......@@ -71,7 +71,6 @@ Ludovic Apvrille, Renaud Pacalet
#endif
class CPU;
class FPGA;
class TMLTransaction;
class TMLCommand;
class TMLTask;
......
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