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Renaud Pacalet / secbus
CeCILL Free Software License Agreement v2.1A hardware / software architecture protecting the external memories of an SoC
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Renaud Pacalet / mli
CeCILL Free Software License Agreement v2.1Yet another Makefile for LaTeX
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Renaud Pacalet / sab4u
CeCILL Free Software License Agreement v2.1A simple example design for Zynq Ultrascale+ based boards.
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Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
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QoE testbed for sampling constrained applications like Skype
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Renaud Pacalet / sab4z
CeCILL Free Software License Agreement v2.1A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.
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