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rtl-ator

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rtl-ator

Project information

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

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Created on

November 08, 2017

Copy SSH clone URLgit@gitlab.enst.fr:sen/dev-projects/rtl-ator.git
Copy HTTPS clone URLhttps://gitlab.telecom-paris.fr/sen/dev-projects/rtl-ator.git